CPE/EE 422/522, Laboratory Assignment 3

Computer Display Interface

(Undergraduate 10% of Final Grade -- Graduate 5% of Final Grade)

 

The purpose of this laboratory project is to give each student the opportunity to understand the basic concepts of computer display techniques and to develop a practical logic design that will drive an EGA type video display. The techniques that are explored here can easily be adapted and applied to drive more modern display elements.

 

Background

The Enhanced Graphics Adapter, EGA, is a video display standard developed by IBM corporation in the late 1980's. It supports 64 distinct colors and allows for a resolution of 640 by 350 picture elements (pixels). All video signals utilize standard digital Transistor-Transistor Logic, TTL voltage levels.

 

EGA monitors contain a color Cathode Ray Tube, CRT. At one end of the CRT is the phosphor screen and at the other end is an electron gun. During normal operation magnetic and electrostatic fields cause a set of electron beams to leave the electron gun and be deflected to the desired position on the phosphor screen of the CRT resulting in that portion of the screen being illuminated in proportion to the intensity of the electrons that strike the phosphor. To achieve color, three types of phosphor are placed on each screen, one for each of the primary colors of red, green, and blue. This phosphor is deposited on the screen in small dots. The screen is then divided up into a set of picture elements (Pixels) with each pixel being composed of three phosphor dots of different types that are placed in close proximity to one another. During normal operation the electron gun produces three separate electron beams which can simultaneously illuminate all three dots at various levels of intensity allowing for a wide range of colors to be created. In the EGA standard, these three electron beams are controlled separately in an on/off manner by applying the appropriate TTL logic level to the associated inputs to the monitor. For each of the three primary colors there are two logical inputs, one which controls whether or not the phosphors for that particular color should be illuminated, and another to select which level of brightness (intensity) that the pixel should have if it is illuminated. By varying the intensity and color bits it is possible for each pixel to be colored in 64 separate ways.

 

Figure 1 shows the pixel configuration for a standard EGA monitor. Notice that the pixels are arranged as a two dimensional array of 350 rows by 640 columns. During standard operation, the electron gun is directed to point to each of the pixels on the screen. As shown in the figure, it begins at the upper left had corner at pixel 0,0 and points to (and illuminates when directed) each pixel along the row going from the left to the right until it points to the last pixel in the row (pixel 639,0). It then retraces back to the left had side of the screen and starts illuminating the selected pixels from left to right along the second row. This process continues this until all the pixels of the 350 rows have been visited in this manner (starting at pixel 0,1). This process is continuous, beginning each time at the upper left most screen postion.



All of this of course occurs at a rate that is much faster than the human eye can observe. In the EGA standard the screen has a 60 HZ refresh rate which means that all pixels are updated once every 1/60 of a second. The EGA monitor uses two synchronization signals. One is the Vertical Sync signal which is used to signal the monitor that a new image (frame) is to be displayed and the other one is the Horizontal Sync which is used to signal the monitor that a new row is to be displayed. The timing for the corresponding vertical and horizontal refresh cycles are shown in Figures 2 and 3.

 



The basic timing for the vertical refresh cycle is shown in Figure 2. The cycle begins with a 595 us negative going vertical sync pulse, after which 350 horizontal refresh cycles occur one for each of the 350 rows to be displayed.

 

Each horizontal refresh cycle, is in turn given by the timing diagram shown in Figure 3. Note that each cycle begins with a 4.92 us positive going horizontal sync pulse, which is to be followed (after a delay of 1.48 us) by the pixel data. This data is the intensity and red/green/blue color bit information for each of the 640 pixels along the corresponding row. The rate at which the horizontal sync pulse is set is 21.85 KHZ, and the pixel data transfer rate is 16.3840 MHZ. During the horizontal sync phase, when the electronic beam is returning to the left most column to begin the next line, all pixel data should be turned off to avoid seeing the horizontal and vertical retrace lines that are shown in Figure 1.


 

Assignment

All students are to develop a design that will clearly display in at least one color on the EGA screen the two or three character initials of her/his name. This design must be demonstrated to the course or lab instructor and fully documented.

 

Since the on-board 25.175MHZ clock on the Altera UP 1 cannot be divide evenly enough to provide stable displays each student will be provided with a 16.3840 MHZ crystal oscillator. This oscillator can be used to generate all synchronization, and pixel data signals. Each station in the rapid prototyping laboratory has an EGA monitor which in turn has a cable that is connected the Altera UP-1 board. All nine EGA signals from the monitor are run out of the cable through separate wires that have connectors on them that can plug directly into the protoboard. Table 1 illustrates the color code convention that has been used.

EGA Connection Information for Rapid Prototyping Laboratory

EGA Function

Wire Color

EGA Function

Wire Color

Ground

Brown

Green

Yellow

Vertical Sync

Black

Green Intensity

Blue

Horizontal Sync

White

Blue

Green

Red

Red

Blue Intensity

Purple

Red Intensity

Orange


Suggested wiring information is presented in a separate handout . If this wiring scheme is not followed then all signals that run into the EGA monitor must be properly buffered using a TTL line driver device, such as a 74xx244. All EGA configurations which do not conform to the handout  must be approved by the laboratory or course instructor before power is applied to the boards.

 

Click here to take VHDL template ( .vhd )

TBD